FC2カウンター FPGAの部屋 Vivado シミュレータでDPI-C を使用してZynq VIPを使う2

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Vivado シミュレータでDPI-C を使用してZynq VIPを使う2

Vivado シミュレータでDPI-C を使用してZynq VIPを使う1”の続き。

前回は、Vivado 2017.2 で Base Zynq サンプル・プロジェクトを作成して、一度シミュレーションを実行し、テストベンチをSystemVerilog ファイルに変更し、シミュレーション用のディレクトリにDPI-C を実行するC ファイルを追加した。今回は、コンパイル、エラボレートを行う。

~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav には、compile.sh ができていた。
DPI_examples_14_170813.png

compile.sh を zynq_dpi.c をコンパイルするように変更する。
DPI_examples_17_170813.png

最後に xsc zynq_dpi.c を追加した。これで、zynq_dpi.c をコンパイルする。
次に、tb_vlog.prj にコンパイルするファイルやオプションが書いてあるので、zynq_tb.sv をコンパイルするように書き換えた。
DPI_examples_18_170813.png

./compile.sh を実行してコンパイルを行った。
DPI_examples_19_170813.png
DPI_examples_20_170813.png

コンパイルのログを貼っておく。

masaaki@masaaki-VirtualBox2:~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav$ ./compile.sh
xvlog -m64 --relax -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_14 -L xil_common_vip_v1_0_0 -L axi_vip_v1_0_2 -L axi_vip_v1_0_1 -prj tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_processing_system7_0_0/sim/base_zynq_processing_system7_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module base_zynq_processing_system7_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_blk_mem_gen_0_0/sim/base_zynq_blk_mem_gen_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module base_zynq_blk_mem_gen_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_xbar_0/sim/base_zynq_xbar_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module base_zynq_xbar_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_auto_pc_0/sim/base_zynq_auto_pc_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module base_zynq_auto_pc_0
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_auto_pc_1/sim/base_zynq_auto_pc_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module base_zynq_auto_pc_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.srcs/sim_1/imports/base_zynq/zynq_tb.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
xvhdl -m64 --relax -prj tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_axi_gpio_0_0/sim/base_zynq_axi_gpio_0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity base_zynq_axi_gpio_0_0
INFO: [VRFC 10-163] Analyzing VHDL file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_axi_bram_ctrl_0_0/sim/base_zynq_axi_bram_ctrl_0_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity base_zynq_axi_bram_ctrl_0_0
INFO: [VRFC 10-163] Analyzing VHDL file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/ip/base_zynq_rst_ps7_0_50M_0/sim/base_zynq_rst_ps7_0_50M_0.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity base_zynq_rst_ps7_0_50M_0
INFO: [VRFC 10-163] Analyzing VHDL file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.ip_user_files/bd/base_zynq/hdl/base_zynq.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity m00_couplers_imp_QHT96L
INFO: [VRFC 10-307] analyzing entity m01_couplers_imp_11WP2HX
INFO: [VRFC 10-307] analyzing entity s00_couplers_imp_1JB4A1T
INFO: [VRFC 10-307] analyzing entity base_zynq_ps7_0_axi_periph_0
INFO: [VRFC 10-307] analyzing entity base_zynq
INFO: [VRFC 10-163] Analyzing VHDL file "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.srcs/sources_1/bd/base_zynq/hdl/base_zynq_wrapper.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity base_zynq_wrapper
Running compilation flow
Done compilation
Done linking: "/home/masaaki/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav/xsim.dir/xsc/dpi.so"
masaaki@masaaki-VirtualBox2:~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav$


~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav/xsim.dir/xsc にdpi.so と zynq_dpi.lnx64.o ができていた。
DPI_examples_21_170813.png

~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav ディレクトリを示す。
DPI_examples_22_170813.png

さて、次にエラボレートを行う。
elaborate.sh を開いて、-sv_lib dpi を追加した。
DPI_examples_23_170813.png

./elaborate.sh を実行した。
DPI_examples_24_170813.png
DPI_examples_25_170813.png

エラボレートのログを貼っておく。ただし、Xilinx 社のIPのワーニングは長すぎるので削除した。

masaaki@masaaki-VirtualBox2:~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav$ ./elaborate.sh
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab -wto 429c07435a554e888bf42dfaf10910cc --debug typical --relax --mt 8 -L axi_infrastructure_v1_1_0 -L xil_common_vip_v1_0_0 -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_14 -L axi_vip_v1_0_2 -L axi_vip_v1_0_1 -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_15 -L blk_mem_gen_v8_3_6 -L axi_bram_ctrl_v4_0_11 -L proc_sys_reset_v5_0_11 -L generic_baseblocks_v2_1_0 -L axi_register_slice_v2_1_13 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_12 -L axi_crossbar_v2_1_14 -L axi_protocol_converter_v2_1_13 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_behav xil_defaultlib.tb xil_defaultlib.glbl -log elaborate.log -cc gcc -sv_lib dpi
Using 8 slave threads.
Starting static elaboration

Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
WARNING: [XSIM 43-3447] Restricting number of parallel compilation jobs to 4 to avoid system resource limitations.
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package unisim.vcomponents
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package axi_bram_ctrl_v4_0_11.axi_bram_ctrl_funcs
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package ieee.std_logic_unsigned
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package axi_lite_ipif_v3_0_4.ipif_pkg
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.sng_port_arb [\sng_port_arb(c_s_axi_addr_width...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.wrap_brst [\wrap_brst(c_axi_addr_width=13,c...]
Compiling architecture muxcy_v of entity unisim.MUXCY [muxcy_default]
Compiling architecture muxcy_l_v of entity unisim.MUXCY_L [muxcy_l_default]
Compiling architecture xorcy_v of entity unisim.XORCY [xorcy_default]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(0,15)\]
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture imp of entity axi_bram_ctrl_v4_0_11.SRL_FIFO [\SRL_FIFO(c_data_bits=12,c_depth...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.wr_chnl [\wr_chnl(c_axi_addr_width=13,c_a...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.rd_chnl [\rd_chnl(c_axi_addr_width=13,c_a...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.full_axi [\full_axi(c_s_axi_addr_width=13,...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.axi_bram_ctrl_top [\axi_bram_ctrl_top(c_bram_addr_w...]
Compiling architecture implementation of entity axi_bram_ctrl_v4_0_11.axi_bram_ctrl [\axi_bram_ctrl(c_memory_depth=20...]
Compiling architecture base_zynq_axi_bram_ctrl_0_0_arch of entity xil_defaultlib.base_zynq_axi_bram_ctrl_0_0 [base_zynq_axi_bram_ctrl_0_0_defa...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.address_decoder [\address_decoder(c_bus_awidth=9,...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.slave_attachment [\slave_attachment(c_ard_addr_ran...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.axi_lite_ipif [\axi_lite_ipif(c_s_axi_addr_widt...]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_single_bit=0,c_vecto...]
Compiling architecture imp of entity axi_gpio_v2_0_15.GPIO_Core [\GPIO_Core(c_aw=9,c_gpio_width=4...]
Compiling architecture imp of entity axi_gpio_v2_0_15.axi_gpio [\axi_gpio(c_family="zynq",c_gpio...]
Compiling architecture base_zynq_axi_gpio_0_0_arch of entity xil_defaultlib.base_zynq_axi_gpio_0_0 [base_zynq_axi_gpio_0_0_default]
Compiling module blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6_output_stage(...
Compiling module blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6_output_stage(...
Compiling module blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6_softecc_outpu...
Compiling module blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6_mem_module(C_...
Compiling module blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6(C_FAMILY="zyn...
Compiling module xil_defaultlib.base_zynq_blk_mem_gen_0_0
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ge...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ge...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_fm...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ar...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ss...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_sp...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_dd...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_oc...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_oc...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_re...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_re...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_if(C_AXI_PROTOCOL...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_onehot_to_binary(...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_srl_rtl(C_A_WIDTH...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_axic_reg_srl_fifo...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_thr...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_syn...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_axi...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_syn...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_syn...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_cor...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_rep...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_top...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_top(C_AXI_PROTOCO...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ax...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ax...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_if(C_AXI_PROTOCOL...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_onehot_to_binary(...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_srl_rtl(C_A_WIDTH...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_axic_reg_srl_fifo...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_thr...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_axi...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_syn...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_cor...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_rep...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_top...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_top(C_AXI_PROTOCO...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ax...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ax...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_if(C_AXI_PROTOCOL...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_axi...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_syn...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_cor...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_rep...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_top...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_top(C_AXI_PROTOCO...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_af...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_af...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_af...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_in...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_af...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_if(C_AXI_PROTOCOL...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_onehot_to_binary(...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_srl_rtl(C_A_WIDTH...
Compiling module smartconnect_v1_0.sc_util_v1_0_2_axic_reg_srl_fifo...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_thr...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_axi...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_cor...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_rep...
Compiling module axi_protocol_checker_v1_1_14.axi_protocol_checker_v1_1_14_top...
Compiling module axi_vip_v1_0_2.axi_vip_v1_0_2_top(C_AXI_PROTOCO...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1_ax...
Compiling module axi_vip_v1_0_1.processing_system7_vip_v1_0_1(C_...
Compiling module xil_defaultlib.base_zynq_processing_system7_0_0
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_axi2ve...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_vector...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axi_r...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_axi2ve...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_vector...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axi_r...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_b...
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_a...
Compiling module xil_defaultlib.base_zynq_auto_pc_0
Compiling architecture structure of entity xil_defaultlib.m00_couplers_imp_QHT96L [m00_couplers_imp_qht96l_default]
Compiling architecture structure of entity xil_defaultlib.m01_couplers_imp_11WP2HX [m01_couplers_imp_11wp2hx_default]
Compiling module axi_protocol_converter_v2_1_13.axi_protocol_converter_v2_1_13_a...
Compiling module xil_defaultlib.base_zynq_auto_pc_1
Compiling architecture structure of entity xil_defaultlib.s00_couplers_imp_1JB4A1T [s00_couplers_imp_1jb4a1t_default]
Compiling module generic_baseblocks_v2_1_0.generic_baseblocks_v2_1_0_carry_...
Compiling module generic_baseblocks_v2_1_0.generic_baseblocks_v2_1_0_compar...
Compiling module generic_baseblocks_v2_1_0.generic_baseblocks_v2_1_0_compar...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_addr_decode...
Compiling module generic_baseblocks_v2_1_0.generic_baseblocks_v2_1_0_mux_en...
Compiling module unisims_ver.SRLC32E_default_1
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_ndeep_srl(...
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_axic_srl_f...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_si_transact...
Compiling module generic_baseblocks_v2_1_0.generic_baseblocks_v2_1_0_mux_en...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_si_transact...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_splitter
Compiling module unisims_ver.SRLC32E_default
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_ndeep_srl(...
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_axic_reg_s...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_wdata_route...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_wdata_mux(C...
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_axic_srl_f...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_axi2ve...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axic_...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_vector...
Compiling module axi_register_slice_v2_1_13.axi_register_slice_v2_1_13_axi_r...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_wdata_mux(C...
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_ndeep_srl(...
Compiling module axi_data_fifo_v2_1_12.axi_data_fifo_v2_1_12_axic_srl_f...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_addr_arbite...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_decerr_slav...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_crossbar(C_...
Compiling module axi_crossbar_v2_1_14.axi_crossbar_v2_1_14_axi_crossba...
Compiling module xil_defaultlib.base_zynq_xbar_0
Compiling architecture structure of entity xil_defaultlib.base_zynq_ps7_0_axi_periph_0 [base_zynq_ps7_0_axi_periph_0_def...]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_vector_width=2,c_mtb...]
Compiling architecture srl16e_v of entity unisim.SRL16E [\SRL16E(init="1111111111111111")...]
Compiling architecture srl16_v of entity unisim.SRL16 [\SRL16(init="1111111111111111")(...]
Compiling architecture imp of entity proc_sys_reset_v5_0_11.lpf [\lpf(c_ext_rst_width=4,c_aux_rst...]
Compiling architecture imp of entity proc_sys_reset_v5_0_11.upcnt_n [\upcnt_n(c_size=6)\]
Compiling architecture imp of entity proc_sys_reset_v5_0_11.sequence_psr [sequence_psr_default]
Compiling architecture imp of entity proc_sys_reset_v5_0_11.proc_sys_reset [\proc_sys_reset(c_family="zynq",...]
Compiling architecture base_zynq_rst_ps7_0_50m_0_arch of entity xil_defaultlib.base_zynq_rst_ps7_0_50M_0 [base_zynq_rst_ps7_0_50m_0_defaul...]
Compiling architecture structure of entity xil_defaultlib.base_zynq [base_zynq_default]
Compiling architecture structure of entity xil_defaultlib.base_zynq_wrapper [base_zynq_wrapper_default]
Compiling module xil_defaultlib.tb
Compiling module xil_defaultlib.glbl
Compiling package axi_vip_v1_0_2.axi_vip_v1_0_2_pkg
Compiling package xil_common_vip_v1_0_0.xil_common_vip_v1_0_0_pkg
Compiling package std.std
Compiling package smartconnect_v1_0.sc_util_v1_0_2_pkg
Waiting for 4 sub-compilation(s) to finish...
0 sub-compilation(s) remaining...
Built simulation snapshot tb_behav
masaaki@masaaki-VirtualBox2:~/Vivado/zynq_base_ex_172/zynq_base_ex_172.sim/sim_1/behav$


Vivado シミュレータでDPI-C を使用してZynq VIPを使う3”に続く。
  1. 2017年08月15日 06:00 |
  2. シミュレーション
  3. | トラックバック:0
  4. | コメント:0

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